/*
*	This is the regisiter between Execute and Memory
*	
*/

//TODO untested

module Reg_EM(
	//Input Signal
	RegWriteIn,
	MemtoRegIn,
	MemWriteIn,
	ALUOutIn,
	WriteDataIn,
	WriteRegIn,
	
	//Output Signal
	RegWriteOut,
	MemtoRegOut,
	MemWriteOut,
	ALUOutOut,
	WriteDataOut,
	WriteRegOut,
	
	//Clock Signal
	CLK,
	EN
);
	input RegWriteIn,MemtoRegIn,MemWriteIn,CLK,EN;
	input[31:0] ALUOutIn,WriteDataIn;
	input[4:0] WriteRegIn;
	
	output RegWriteOut,MemtoRegOut,MemWriteOut;
	output[31:0] ALUOutOut,WriteDataOut;
	output[4:0] WriteRegOut;

	reg RegWriteOut,MemtoRegOut,MemWriteOut;
	reg[31:0] ALUOutOut,WriteDataOut;
	reg[4:0] WriteRegOut;
	integer ClockCount;
	
	//initial
	initial begin
		RegWriteOut	=	0;
		MemtoRegOut	=	0;
		MemWriteOut	=	0;
		ALUOutOut	=	0;
		WriteDataOut	=	0;
		WriteRegOut	=	0;
		ClockCount	=	0;
	end
	
	//when CLR come through a posedge begin work
	always @(posedge CLK) begin
		if(EN == 1 && ClockCount == 0) begin
			RegWriteOut		<=	RegWriteIn;
			MemtoRegOut		<=	MemtoRegIn;
			MemWriteOut		<=	MemWriteIn;
			ALUOutOut		<=	ALUOutIn;
			WriteDataOut	<=	WriteDataIn;
			WriteRegOut		<=	WriteRegIn; 
		end
		ClockCount = (ClockCount + 1)%2;
	end
	
endmodule
